A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.

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> Content addressable memory having reduced power consumption

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