Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are operated alternately to obtain an apparent operating speed equivalent to that of a CPU. Read clock generating circuits are placed in close proximity to clock input pins of respective ones of the flash ROMs and supply the flash ROMs with read clocks obtained by dividing down the frequency of a system clock. Delay ascribable to wiring is eliminated from the read clocks as a result.

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> Memory allocation using a memory address pool

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